With the widespread application of switching power supplies, the rectification and filtering processes of switching power supplies generate a large amount of high-order harmonics, causing severe distortion of the current waveform, which in turn leads to electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues. Therefore, power factor correction (PFC) technology has emerged.
PFC technology is designed to correct the current waveform so that it remains in phase with the voltage waveform, thereby improving the power factor and reducing harmonic interference.On the other hand, power supplies typically need to comply with CISPR32 or EN55032 standards. The primary purpose of these standards is to ensure that information technology equipment does not cause harmful interference to other devices during operation, while also being able to resist external electromagnetic interference. CISPR32/EN55032 testing is divided into two categories: conducted interference and radiated interference.
Additionally, the standards are divided into two categories based on the type of product usage environment. Any equipment intended primarily for residential environments must comply with Class B limits, while all other equipment must comply with Class A limits. Figure 1 shows the conducted interference limit curve.
Figure 1. CISPR32/EB55032 Conducted Interference Limit Curve
Early PFC technology primarily utilized a bridge rectifier combined with a boost-type PFC converter (Boost PFC Converter). Due to the presence of the bridge rectifier, there are always two diodes conducting simultaneously during the operation of the converter. In high-power applications, this fixed loss increases with the rise in current, thereby affecting further improvements in efficiency.
Nowadays, the power supply market is responding to global carbon reduction initiatives by setting efficiency goals focused on higher performance, reduced losses, energy savings, cost reduction, and increased system capacity. Totem-pole PFC, with its simple structure and fewer components, can provide higher power density within a smaller footprint. Additionally, wide-bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC) are being introduced into designs. These materials feature lower conduction resistance and faster switching speeds, further enhancing efficiency and power density. As a result,Totem-pole PFC is widely used in various high-performance and high-power-density power systems.such as server power supplies, 5G communication power supplies, electric vehicle chargers, and industrial power supplies.
The Totem-Pole PFC is composed of two half-bridge switches. One half-bridge acts as a rectifier bridge, responsible for the return path from the negative terminal of the capacitor to the input ground, and can use standard low RDS(ON) MOSFETs. The other half-bridge handles the charge and discharge switching of the Boost converter, which can be composed of power transistors such as SiC/GaN FETs with short reverse recovery times.
As shown in Figure 2, the working principle of the circuit is mainly divided into two parts: the positive half-cycle and the negative half-cycle. Positive half-cycle (VAC > 0): When Q1 is turned on, the inductor current rises, and the inductor stores energy. Then, Q1 turns off, and the inductor begins to release energy, causing the inductor current to decrease. At this time, the body diode of Q2 conducts forward during the dead time. Subsequently, Q2 turns on, reducing power loss caused by the body diode. During the positive half-cycle, SD2 remains in the normally open state, while SD1 remains in the normally closed state. Negative half-cycle (VAC < 0): When Q2 is turned on, the inductor current rises, and the inductor stores energy. Then, Q2 turns off, and the inductor begins to release energy, causing the inductor current to decrease. At this time, the body diode of Q1 conducts forward during the dead time. Subsequently, Q1 turns on, reducing power loss caused by the body diode. During the negative half-cycle, SD1 remains in the normally open state, while SD2 remains in the normally closed state.
Figure 2. Working Principle of Totem-Pole PFC
However, the Totem-Pole PFC, while improving efficiency and power density, also faces the issue of electromagnetic interference (EMI). Among these, common-mode noise is the primary source of interference in this topology. It is typically caused by high-frequency noise generated from the high-speed switching of power components. This noise can couple to the frame ground (FG) through parasitic capacitance, thereby generating common-mode noise.
As shown in Figure 3, the high-frequency switching on and off actions of Q1 generate high voltage changes (dv/dt), becoming a noise source. The noise current flows through the parasitic capacitance Cp and then passes through the LISN. To reduce the noise current flowing through the LISN, a capacitor Cfg can be added between FG and the grounding terminal (GND) of the PFC output capacitor. This capacitor can be considered a Y capacitor, providing low impedance for switching noise.
Figure 3. Noise sources caused by high-frequency switching and their conduction paths
On the other hand, as described in the literature [1], a typical control issue in a totem-pole PFC circuit is the AC voltage zero-crossing switching. When the AC voltage is in the positive half-cycle and approaches the AC zero-crossing point, Q1 acts as the main switch. Due to the very low input voltage, its duty cycle reaches nearly 100% (while Q2's duty cycle is close to 0), and SD1 remains conducting throughout this half-cycle.
When the AC voltage transitions to the negative half-cycle, Q2 acts as the main switch. Due to the very low input voltage during this phase, its duty cycle approaches 100% (while Q1's duty cycle approaches 0%). During this stage, SD2 transitions from being off to conducting. When Q2 turns on, the parasitic output capacitance Coss of SD1 discharges rapidly, which not only generates a reverse inductive current spike but also produces common-mode noise due to the rapid high-voltage change (dv/dt). Figure 4(a) illustrates the conduction path of the common-mode noise at the zero-crossing point. The voltage across SD1, acting as the noise source, is a square wave with an amplitude equal to the output voltage and a frequency identical to the AC input voltage.
Figure 4. Noise sources generated by zero crossing points and their conduction paths
To address the slow reverse recovery performance of traditional MOSFET switches, wide bandgap power semiconductors are typically used in the design of totem-pole PFCs. Onsemi has integrated various power electronic components into a single GaN chip in its wide bandgap power semiconductor (iGaN) technology, enabling the integration of a 650V GaN FET and GaN driver into a single chip.
The key to integration is the ability to reduce latency and eliminate parasitic inductance.Significantly reduce losses associated with switching frequency. As mentioned earlier, to reduce the common-mode noise of the totem-pole PFC, adjustments can first be made to the noise generated by high-frequency switching. onsemi's iGaN allows for adjustments to the dv/dt slope during turn-on. Figure 6(a) shows the peripheral circuit of the NCP58922. By adjusting the Ron resistor in series with VDR, the dv/dt slope during the turn-on of the NCP58922 can be modified, thereby reducing common-mode noise.
Figure 5. iGaN can adjust the dv/dt slope during turn-on through Ron.
On the other hand, to reduce the common-mode noise generated at the zero-crossing point, capacitors C3 and C4 are connected in parallel with the crystal in the slow arm (as shown in Figure 7). This can decrease the rate of voltage change (dv/dt), thereby suppressing common-mode noise [2]. After adding the capacitors, the noise sources near the zero-crossing point not only pass through capacitor Cfg but also through capacitors C3 and C4. Since the capacitance of Cfg is much smaller than that of C3 and C4, the noise current flowing through Cfg is relatively small.
Figure 6. Capacitors C3 and C4 connected in parallel with the crystal on the slow arm.
In addition, another method to reduce the dv/dt slope of the slow leg at the AC zero-crossing point is through a soft-start approach, gradually increasing the duty cycle of the fast leg. Figure 8 illustrates the zero-crossing control mechanism (open loop pulses) of ON Semiconductor's totem-pole PFC controllers (NCP1680, NCP1681) [3]. After the AC passes the zero-crossing point, the Vds voltage across SD1 transitions starting from a smaller duty cycle. Then, the duty cycle is gradually increased, causing Vds to drop from 400V to 0V, while completing the commutation control of the slow leg. The NCP1680 and NCP1681 provide designers with four open loop pulse options, which can be selected based on the output capacitance (Coss) of the slow leg or the PFC inductance value.
Figure 7. The zero-crossing control mechanism of the NCP1680/1 (open loop pulses)
onsemi offers a 500W high-efficiency and high-power-density adapter solution (EVBUM2875).As shown in Figure 8, this solution utilizes a Totem Pole PFC controller (NCP1681) and an LLC controller (NCP13994) to complete the gaming laptop adapter design. Additionally, it incorporates iGaN (NCP58921) to reduce the overall size of the adapter to 183mm*93mm*30mm, increasing the power density to 16W/inch^3.
Figure 8. 500W Gaming Adapter Solution
Additionally, this solution adopts the EMI countermeasures provided earlier: (1) adding a Y capacitor (Cfg) between the FG and the PFC bulk ground terminal, (2) adjusting the on-resistance of the iGaN, (3) paralleling capacitors on the slow arm (C3, C4), and (4) selecting appropriate open-loop pulses to reduce the voltage slope at the zero-crossing point. Figure 9 shows the conducted EMI test results, which meet the CLASS B specifications.
Figure 9. Conducted EMI Test Results