1. Introduction
Since the advent of third-generation semiconductors, they have increasingly become a hot topic in today’s technology field, demonstrating immense potential in areas such as high-speed computing, energy efficiency, and high-frequency communication. With the rapid development of this emerging technology, there is an urgent need to comprehensively evaluate and test its performance to ensure it meets the expected outcomes in practical applications. This article aims to discuss the characteristics of SiC MOSFETs and their requirements for gate drive circuits, while also providing onsemi’s SiC MOSFET drive solutions, offering R&D engineers an additional option for circuit design.
2. Power Losses in MOSFET Components: Sources
(Figure 1) illustrates a circuit using a half-bridge (HB) topology with SiC MOSFETs as power components. The total power loss is primarily composed of conduction losses and switching losses. The conduction losses of the MOSFET are related to the MOSFET’s on-resistance (Rds_on), while the switching losses are associated with parameters such as Qg, Qrr, Ciss, Rg, Eon, Eoff, etc.
Image Source: onsemi website, Author: Bob Card
3. Switching Types: Gate Drive Selections
(Figure 2) explains the optimal gate drive voltages for different power components such as pure Si MOS, IGBT, and SiC MOS:
- For pure Silicon MOS, the gate driver voltage switches between 0V and 10V to achieve optimal efficiency.
- For IGBT, the gate driver voltage switches between 0V and 15V to achieve optimal efficiency.
- For SiC MOS, the gate driver voltage switches between -3V and +18V to achieve optimal efficiency.
- Image Source: onsemi website, Author: Bob Card
(Figure 3) illustrates the efficiency performance of SiC MOS under different gate drive voltage conditions:
- When the gate driver voltage switches between 0V and +15V, the SiC MOS operates normally, but its efficiency does not match the Rds_on performance of pure Silicon MOS, typically performing worse than pure Silicon MOS with the same Rds_on.
- When the gate driver voltage increases to switch between 0V and +18V, efficiency improves compared to 0V to +15V, primarily due to a 25% reduction in conduction losses, a 25% reduction in EON losses, and a 3% reduction in EOFF losses.
- When the gate driver voltage switches between -3V and +18V, efficiency further improves compared to 0V to +18V, mainly due to a 25% reduction in EOFF losses. This improvement is attributed to the negative drive voltage enabling a more complete turn-off of the SiC MOS.
- Image Source: onsemi website, Author: Bob Card
5. The Impact of Negative Bias on EOFF Switching Losses
(Figure 4) uses the onsemi NTH4L022N120M3S SiC MOSFET as an example to illustrate that providing a -3V Vgs voltage compared to 0V Vgs can reduce EOFF switching losses by approximately 100uJ.
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- Image Source: onsemi website, Author: Bob Card
6. SiC MOSFET Turn-On Explanation: (Figure 5)
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- Image Source: onsemi website, Author: Bob Card
7. SiC MOSFET Turn-Off Explanation: (Figure 6)
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- Image Source: onsemi website, Author: Bob Card
8. Calculation of Gate Drive Current iG (First-Order Approximation)
(Figure 7) explains the relationship between gate drive current iG, QG(TOT), and switching speed. This is a preliminary, non-precise calculation that can be referenced when selecting gate drive ICs and SiC MOSFETs. Using onsemi’s NCP51561 Gate Driver IC and NTH4L022N120M3S as examples, the relationship between these parameters can be found in their datasheets.
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- Image Source: onsemi website, Author: Bob Card
9. Conclusion
The gate drive voltage of MOSFETs significantly impacts performance, especially for the increasingly popular SiC MOSFETs, which have higher gate drive voltage requirements compared to pure Silicon MOSFETs. Future design trends will likely standardize gate drive voltage specifications, implying that SiC MOSFETs will gradually replace traditional pure Silicon MOSFETs in high-efficiency, high-power energy conversion applications.